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Bit
8
Name
RXDATAV
Reset
0
Access
R
Description
RX Data Valid
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
7
TXBL
1
R
TX Buffer Level
Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.
6
TXC
0
R
TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmission starts.
5
PABORT
0
R
Pending abort
An abort is pending and will be transmitted as soon as possible.
4
PCONT
0
R
Pending continue
A continue is pending and will be transmitted as soon as possible.
3
PNACK
0
R
Pending NACK
A not-acknowledge is pending and will be transmitted as soon as possible.
2
PACK
0
R
Pending ACK
An acknowledge is pending and will be transmitted as soon as possible.
1
PSTOP
0
R
Pending STOP
A stop condition is pending and will be transmitted as soon as possible.
0
PSTART
0
R
Pending START
A start condition is pending and will be transmitted as soon as possible.
15.5.5 I2Cn_CLKDIV - Clock Division Register
Offset
0x010
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8:0
DIV
0x000
RW
Clock Divider
Specifies the clock divider for the I C. Note that DIV must be 1 or higher when slave is enabled.
2
15.5.6 I2Cn_SADDR - Slave Address Register
Offset
0x014
Reset
Access
Name
Bit Position
2011-04-12 - d0001_Rev1.10
169
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